The present invention generally relates to a method of manufacturing semiconductor memory devices, and more particularly, to a method of manufacturing a flash memory device, to reduce the inter-cell interference of NAND flash memory devices by employing a Self-Aligned Shallow Trench Isolation (SA-STI) process.
In a NAND flash memory device, a plurality of cells for storing data are connected in series to form one string. A drain select transistor and a source select transistor are formed between the cell string and the drain, and between the cell string and the source, respectively. A cell of the NAND flash memory device is formed by forming a gate in which a tunnel oxide film, a floating gate, a dielectric layer, and a control gate are sequentially laminated on a semiconductor substrate and forming junction units at both sides of the gate.
In the NAND flash memory device, the state of the cell is influenced by the operations of neighboring cells. It is therefore very important to constantly maintain the state of the cell. When the state of the cells is changed by the operations of neighboring cells (more particularly, the program operation), this phenomenon is referred to as an “interference phenomenon”. In more detail, the term “interference phenomenon” refers to a phenomenon in which in the case where a second program adjacent to a first cell to be read is programmed, a threshold voltage higher than that of the first cell is read due to the capacitance operation incurred by variation in the charges of the floating gate of the second cell when the first cell is read.
In other words, the interference phenomenon refers to a phenomenon in which the state of an actual cell looks distorted by variation in the state of a neighboring cell even though the charges of the floating gate of the read cell are not changed. The state of the cell is changed by the interference phenomenon. This results in an increased failure ratio and a lower yield. Accordingly, it is effective to maintain constantly the state of the cell in order to minimize the interference phenomenon.
Meanwhile, in the manufacture process of a general NAND flash memory device, portions of the isolation structure and the floating gate are formed by the SA-STI process. The SA-STI process will be described in short below.
After a tunnel oxide film and a first polysilicon layer are formed on a semiconductor substrate, the first polysilicon layer and a predetermined region of the tunnel oxide film are etched. The semiconductor substrate is etched to a predetermined depth, forming a trench. An insulating layer is filled into the trench and a polishing process is performed to form an isolation structure.
A second polysilicon layer is formed on the entire structure. The second polysilicon layer is patterned in such a way to be partially overlapped with the isolation structure, thus forming a floating gate in which the first and second polysilicon layers are laminated. In order to completely remove the etch remnants of the second polysilicon layer, the second polysilicon layer is over-etched. Accordingly, the isolation structure is etched to a predetermined depth. It is therefore necessary to perform sufficient over-etch in order to completely remove the etch remnants of the second polysilicon layer. An amount of the isolation structure that is removed is about 100 Å. After a dielectric layer is formed on the entire structure, a third polysilicon layer for a control gate is formed.
If the flash memory device is fabricated using the SA-STI process as described above, the isolation structure is formed between the first polysilicon layer serving as the floating gate and a neighboring first polysilicon layer. Therefore, interference may occur between the first polysilicon layers.
In addition, the isolation structure is etched to a predetermined depth and the distance between the semiconductor substrate of the active region and the control gate is narrowed accordingly. Accordingly, cycling fail may occur because the semiconductor substrate is influenced by the control gate.